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2005 Microchip Technology Inc.
Preliminary
DS41265A-page 147
PIC16F946
FIGURE 11-11:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
11.4
USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK/SCK/SCL/SEG9 pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in Sleep mode.
Slave mode is entered by clearing bit, CSRC
(TXSTA<7>).
11.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep mode.
If two words are written to the TXREG and then the
SLEEP
instruction is executed, the following will occur:
a)
The first word will immediately transfer to the
TSR register and transmit.
b)
The second word will remain in TXREG register.
c)
Flag bit TXIF will not be set.
d)
When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
e)
If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled, the program will branch to the interrupt
vector (0004h).
When setting up a Synchronous Slave Transmission,
follow these steps:
1.
Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2.
Clear bits CREN and SREN.
3.
If interrupts are desired, then set enable bit
TXIE.
4.
If 9-bit transmission is desired, then set bit TX9.
5.
Enable the transmission by setting enable bit
TXEN.
6.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7.
Start transmission by loading data to the TXREG
register.
8.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
CREN bit
RC7/RX/DT/
RC6/TX/CK/
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
Q3 Q4Q1Q2 Q3Q4Q1Q2Q3Q4
Q2
Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4
‘0’
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
‘0’
Q1Q2Q3Q4
SDI/SDA/SEG8
SCK/SCL/SEG9
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